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ANALOG DEVICES fAX-ON-DEHAND HOTLINE
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Page
23
W
I
ANALOG DEVICES
FUNCTIONAL
12-Bit,100MSPS UtAConverters
AD97121AD9713
I
FEATURES 100 MSPS Update Rate ECL/TTL Compatibility Low Glitch Impulse: 100 pV-s Fast Settling: 30 ns to %1 LSB Low Power: 700 mW APPUCA TlONS ATE Signal Reconstruction Arbitrary Waveform Generators Digital Synthesizers Signal Generators
BLOCK DIAGRAM
AD9712/AD9713
OBS
rn
;1" CONTROL .!!.I CONTROL m ANALOG RETURN 113
GENERAL DESCRIPTION The AD9712 and AD9713 are I2-bit, high speed digitalto-analog converters constructed in an advanced oxide isolated bipolar process. The AD9712 is an ECL-compatible device featUring update rates of 100 MSPS minimum; the TTLcompatible AD9713 will update at 80 MSPS minimum.
Designed for direct digital synthesis, waveform reconstruction, and high resolution imaging applications, both devices feature low glitch impulse of 100 pV-s; and fast settling times of 30 ns to :!:1 LSB. Both units are characterized for dynamic performance, and have excellent harmonic suppression.
OLE
~2o)oo REFERENCEY OUT L
The AD9712 and AD9713 are available in 28-pin plastic DIPs and PLCCs, with an operating temperature range of 0 to + 70C. Contact the factory for availability of military-grade devices.
c
0
Q' a
Q' Q
TE
~
w
o(191 YcONTROL I AMP IN
a:
C)
%
..
m:
iii
~ <> ~ 5~ C
;i
~
61 LATCH ENABLE
!I DIGITAL+V. REFERENCE GROUND
221 REFERENCE
GROUND
~
:2J REFERENCE OUT AMP IN AMP OUT IN
REFERENCE OUT
AMP IN
191 CONTROL
REFERENCE
,:' ,
51 ANALOG-V.
9 :!
..
'"
I- ,., Bwo
~
5
~.. ~ c:
II!
0
a. %::E
~
0 0
Plastic DIPPinout Designations (Top View)
PLCC Pinout Designations
REV.A
Information furnished by Analog Devices is believed to be accurate and reliable. However. no responsibility is assumed by Analog Devices for its use. nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way. P.O. Box 9106. Norwood. MA 02062-9106 Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 We5t CQut Central Atlantic: 714/641-9391 214/231-5094 215/643.7790
RNRLOGDEVICES fRX-ON-DEnRND HOTLINE
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2~
AD9712/AD9713 -SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS! Positive Supply Voltage (+Vs)(AD9713 Only) . . . . . . . .+6 V Negative Supply Voltage (-Vs) (AD9712andAD9713) 7V DAC Outputs to ANALOG RETURN . . . . . .+0.5V to -2 V Digital Input Voltages (D1-D12' LATCH ENABLE) AD9712 0Vto-Vs AD9713 0Vto+Vs Internal Reference Output Current. . . . . - 20 JLAto + 500 fLA Control Amplifier Input Voltage Range . . . . . . . .0Vto -4 V ControlAmplifierOutputCurrent .:!:2.5mA REFERENCE IN Voltage Range. . . . . . . . . .-3.7 V to -Vs Analog Output Current (lOUT or lOUT) .30 mA Operating TemperatUre Range AD9712]NIJP Oto+70DC AD9713]N/]P Oto+70DC Maximum Junction Temperature2 . . . . . . . . . . . . . . .+IS0.C Lead TemperatUre (Soldering, 10 seconds) . . . . . . . . .+ 300DC Storage TemperatUre Range .-65C to + IS0DC
ELECTRICALCHARACTERISTICS (-Vs
= -5.2
V;+vs
OBS
Parameter (Conditions) RESOLUTION Temp DC ACCURACY Differential Nonlinearity Q) Integral Nonlinearity Q) (external); R$ET
=1.5 kG, unlessotherwisenoted)
Max AD9713JNIJP MiD Typ 12 1.2
=+5 V(AD9713 Only); CONTROL
AMP
IN
=-1.2 V
Units Bits LSB LSB LSB LSB IJoA IJoA % % p.ArC
Test AD9112JN/JP Level MiD Typ 12 1.2
Max
OLE
2.0 4.0 3.0 4.0 0.5 4.0 1.5 5.0 8.5 11.0 0.5 4.0 0.03 0.03 -1.13 -1.11
2.0 4.0 3.0 4.0 1.5 5.0
- 1.26
- 1.39 -1.41
-1.13 -1.11
-1.26
300 50 300 3 40 20.48 -1.2 2.0 100 2.5 30 110 30 30 8 100 400 3 2 +3 3.0 -1.2 2.0 80
300 50 300 3 40 20.48 2.5 30 90 30 30 11 100 400 3 2
TE
8.5
11.0
- 1.39 V
-1.41
V IJoV/oc kO kHz
kf! MHz mA V kf! pF M,SPS ns ns ns pV-s V/s ns ns
+3 3.0
-2-
REV.A
RNRLOGDEVICES fRK-ON-DEHRND HOTLINE
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AD9712/AD9713
Parameter (Conditious)
DIGITAL INPUTS Logic "I" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitallce Input SetUp Time (t8)12 Input Hold Time (tiVU Latch Pulse Width (tLPW) (Transparent) AC LINEARITY1. Spurious-Free Dynamic Range POWER SUPPL ylS Positive Supply Current (+5.0 V) Negative Supply Current (-5.2 V) Temp Full Full Full Full + 25C + 25C + 25"C +25"C +25C
+2S"C
Test Level VI VI VI VI V V V V V I VI I VI V I
AD97UJNIjP MiD Typ
Max
AD9713JNIjP MiD Typ 2.0
Mu.
Units V V f.LA pF fiS fiS ns dBc
-1.0
-0.8 -1.7
3 3 3 2.5 -60
-1.5
20 10 3 3 3 4 -55 10
0.8
20 600
OBS
Nominal Power Dissipation Power Supply Rejection Ratio (PSRR)16 +25C NOTES
14Update rate s50
It :t5%
Full + 25"C Full +25"C
130 676 50
160 170 350
135 726 50
20 23 165 175 350
mA mA mA mA mW IJ.AN
'AbsolUte maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functioual operability is DOtnco:ssarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2"fypicaI thcrmal impedances: 28-pin plastic DIP 8J/\ = 4row; 8JC = 7"CIW; 28-pin PLCC 9,/\ = 48C/Wj 8Jc = IOOCJW. 3Measured as error of me ratio of full-scale current to current throush RSET (160 IJ.Anominal); ratio is nominally 128. 4Pu11-scale variattous &moor devices are more severe when driving REFERENCE IN directly. 'Frequ~ at which a 3 dB reduction in output of DAC is observed; RL = 50 OJ 50% modulation at midscale. when using internal amplifier. 6Based on Ips = 128 (V~) 70utpUt settJin& to 0.1%. 'Measured at midscale transition, (0 :to.O24%. 'Measured from falling edge of LATCH ENABLE signal to 50% point of full.scale transition. "'Glitch impuJlie combines me absolute value of positive and negarive transitions operating in latched mode. uMcasurcd wim RL = SO 0 and DAC operating in latched mode. "Data must remain stable prior (0 falling edge of LATCH ENABLE signal for specified time. 13Data must remain stable after rising edge of LATCH ENABLE signal for specified time.
MSPS;
of
OLE
or AD9713) using external reference.
output
frequency
only)
= 5 MHz.
and
"Supply
16Mcasured
voltages should remain stable within :t5% for normal operation.
+ V s (AD9713
-
V s (AD9712
TE
Specifications subject to chance withoUt ponce.
EXPLANATION Level
I
OF TEST LEVELS Model
ORDERING GUIDE Package Option. N-28 P-28A N-28 P-28A
-
II
-
100% production
tested.
Description ECL-Compatible Plastic DIP ECL-Compatible PLCC ITL-Compatible Plastic DIP ITL-Compatib1e PLCC
DIP; P
100% production tested at + 25C. and sample tested at
specifiedtemperatures. III - Sampletested only. IV - Parameteris guaranteedby design and characterizationtesting. V Parameter is a typical value only.
VI
AD9712JN AD9712JP AD97I3JN AD9713JP
*N
- All devices arc 100% production
= Plastic
= Plastic
Leaded Chip Carrier.
tested at +25C. 100% production tested at temperatUre extremes for extended temperature devices; sample tested at temperature exttcmes for commercial/industrial devices.
REV. A
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ANALOGDEVICES fAX-ON-DEMAND HOTLINE
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AD9713/AD9713
AD911Z1AD9713 DESCRIPTIONS PIN Pia Fanctioll No. Name
1-10 11 12 13 D2-D11 D12 (LSB) DIGITAL -Vs ANALOG RETURN Ten of twelve digital input bits. Least Significant Bit (LSB) of digital input word. One of two negative digital supply pins; nominally -5.2 V. Analog ground retUrn. This point and the reference side of the DAC load resistors should be connected to the same potential (nominally ground). Analog current output; full-scale output occurs with digital inputs at all "I." One of two negative analog supply pins; nominally -5.2 V. Complementary analog current output; zero scale output occurs with digital inputs at all "1." Normally connected to CONTROL AMP OUT (Pin 18). Direct line to DAC current switch network. Voltage changes at this point have a direct effect on the full-scale output. Full-scale current output"" 128 (Reference voltageIRsET) when using internal amplifier. Normallyoonnected to REFERENCE IN (pin 17). Output of internal control amplifier, which provides a temperature oompensated drive level to the current switch network.
connected to external reference. Full-scale current out
14 15 16 17
loUT ANALOG -Vs loUT REFERENCE IN
OBS
18 CONTROL AMP OUT 19 CONTROL AMP IN 20 21 22 23 24 REFERENCE OUT DIGITAL -Vs REFERENCE GROUND DIGITAL +Vs RsET
Normally connected to REFERENCE OUT (pin 20) if not
(Reference voltageIRsET) when using internal amplifier.
Normally connected to CONTROL AMP IN (pin 19). Internal voltage reference, nominally -1.26 V.
One of two negative digital supply pins; nominally
Ground return for the internal voltage reference and amplifier.
OLE
=
128
- 5.2 V.
Positive digital supply pin; used only on the AD9713; nominally +5V. Connection for external resistance reference. Full-scale current out 128 (Reference voltagelRsET) when using internal amplifier.
TE
LATCHPULSEWIOTIf
=
25 26 27 28
ANALOG -Vs LATCH ENABLE DIGITAL GROUND D1 (MSB)
One of two negative analog supply pins; nominally -5.2 V. Transparent latch coDtrolline. Digital ground retUrn. Most Significant Bit (MSB) of digital input word.
LATCH ENABLE
LATCH ENABLE
OUTPUT ERROR
DATA HOUrS
OUTPUT
./
t..- t ..
I ST t I'D
t.--
INPUTSETUPTIIE
INPUT HOLD TIME OUT'POT SETTUHO TIME
OUT'POT PROPAGA11ON DELAY
-
AD97121AD9713 Timing Diagram
-4-
REV.
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AD9712/AD9713
THEORY AND APPUCATIONS The AD9712 and AD9713 high speed digital-to-analog conveners utilize Most Significant Bit (MSB) decoding and segmentation techniques to reduce glitch impulse and maintain linearity without trimming. As shown in the functional block diagram, the design is based on four main subsections: the DecoderlDriver circuits, the Transparent Latches, the Switch Network and the Control Amplifier. An internal band-gap reference is also included to allow operation with a minimum of external components. Digital Inputs The AD9712 employs single-cnded ECL-compatible inputs for data inpUtS DI-D12 and LATCH ENABLE. The internal ECL midpoint reference is designed to match 10K ECL device thresholds. On the AD9713, a TTL translator is added at each input; with this exception, the AD9712 and AD9713 are identical. greater accuracy or better temperature stability is required, an external reference can be utilized. The AD589 reference shown in Figure I features :t 10 ppm?C drift over temperatUres from 0 to +70C.
A09712 A09713
:II1)CON'TROl 4MP IN
R, ::11kl)
-VI
Figure 1. Use of A 0589 8S External Reference Two modes of multiplying operation are possibl~ with the AD97121AD9713. Signals with bandwidths up to 400 kHz and input swings from -0.1 V to -1.2 V can be applied to the CONTROL AMP input as shown in Figure 2. Because the control amplifier is internally compensated, the 0.1 J.LFcapacitor at Pin 17 can be eliminated to maximize the multiplying bandwidth. However, it should be noted that settling time for changes to the digital inputs will be degraded.
OBS
In the DecoderlDriver section, the four MSBs (DcDJ are decoded to 15 "thermometer code" lines. An equalizing delay is included for the eight Least Significant Bits (LSBs) and LATCH ENABLE. This delay minimizes data skew, and data setup and hold times at the latch inputs; this is important when operating the latches in the transparent mode. Without the delay, skew caused by the decoding circuits would degrade glitch impulse. The latches operate in their transparent mode when LATCH ENABLE (Pin 26) is at logic level "0." The latches can be used to synchronize data to the current switches by applying a narrow LATCH ENABLE pulse with proper data setup and hold times as shown in the timing diagram. With an external transparent latch at each data input clocked out of phase with the DAC, the AD97121AD9713 operates in a master slave (edge-triggered) mode.
OLE
.IJ.6Vlo.l.2V
Although the AD97121AD9713 chip is designed to provide isolation from digital inputs to the outputs, some coupling of digital transitions is inevitable, especially with TTL or CMOS inputs applied to the AD9713. Digital feedthrough can be reduced by forming a low-pass filter using a resistor in series with the capacitance of each digital input. References As shown in the functional block diagram, the internal band-gap reference, control amplifier and reference input are pinned out for maximum user flexibility when setting the reference. When using the internal reference, REFERENCE OUT (Pin 20) should be connected to CONTROL AMP IN (pin 19). CONTROL AMP OUT (pin 18) should be connected to REFERENCE IN (Pin 17) through an 18 n resistor. A 0.1 J.LF ceramic capacitor from Pin 17 to -Vs (pin 15) improves settling by decoupllng switching noise from the current sink base line. A reference current cell provides feedback to the control amp by sinking current through Rsn (Pin 24). Full-scale output current is determined by the voltage at CONTROL AMP IN (VREF)and Rsn according to the equation:
lOUT IPS)
181l
TE
AD9712 AD9713
-vo
Figure 2. Low Frequency Multiplying Circuit The REFERENCE IN pin can also be driven directly for wider bandwidth multiplying operation. The analog signal for this mode of operation must have a signal swing in the range of -4 V to -5.2 V. This can be implemented by capacitively coupling into REFERENCE IN an ac signal and establishing a de bias of -4.0 V to -5.2 V, as shown in Figure 3; or by driving REFERENCE IN with a low impedance op amp whose signal swing is limited to the stated range.
4k1l
ANAl~
>
O.I~FI 1.2k11
= VREFIRsET x 128.
-V.
The internal reference is nominally - 1.26 V with a tolerance of :t 10% and typical drift over temperature of 300 J.Lrc. If v
Figure 3. Wideband Multiplying Circuit -5-
REV. A
ANALOG DEVICES fAX-ON-DEMAND HOTLINE
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AD9712/AD9713
Outputs The Switch Network controls complementary current outputs lOUT and lOUT' As indicated earlier, DcD. are decoded into IS "thermometer code" lines which drive matched current sources. Ds and D6 control weighted current sources; and D7-D12 are applied to the R-2R network. This segmentation reduces frequency domain errors due to' glitch impulse. Current is steered to either lOUT or lOUT in proportion to the digital input code. The sum of the two currents is always equal to the full-scale output current minus one LSB. The current output can be converted to a voltage by resistive loading as shown in Figure 4. Both louT and lOUT should be loaded equally for best overall performance. The voltage which is developed is the product of the output current and the value of the load resistor. the DAC output as shown in Figure 5. Reducing DAC full-scale outpUt current degrades both linearity and settling time; therefore, the current divider method is preferable.
.V."'
R"
v"'"
RL
V'OLL 8C.ILE ~ .5V
Yu.a""
RL
=-5V
OBS
-uv
Figure 5. IN Conversion
Using Current Feedback Amp
O.'"F*
eeL
DRIVE LOGIC
OLE
RLIFS
The DAC output is not clamped at virtual ground in this configuration because of the series resistance RFF' The value of RFF is selected according to the equation:
-
V Full Seal<
R
RFF
=
FB
+ I OFF R L
V Full Scale
R FB
As an example, assume the following conditions: RL 0=50 n RFB = 1.5 kG
IFs = 20.48 mA
RFB
--VZerosC'.oIeI OFF- 33 mA . Given these conditions, RFF
=
103.6 fl
TE
+ I OFF
S'lSTI!M CAOuICI
Figure 4. Typical Resistive Load Connection
When operating at the nominal full.scale current of 20.48 mA, the voltage swing will be from 0 to -1.024 V across SOfl resistors. Bipolar outputs are possible by sourcing a current equal to half the DAC full-scale current into the load resistor. An alternate method of converting the current oUtput to voltage is by driving the summing node of an operational amplifier directly with a feedback resistor selected according [0 "the equation: RFS = VOUT(FSI / lOUT (FS) A current feedback amplifier such as the AD9610 offers signifi. cantly faster settling and greater bandwidth than a conventional voltage feedback op amp. The feedback resistor for the AD9610 must be 1.5 kfl or greater to maintain stability. This value for RFB' along with the 20.48 mA full-scale output current, results in a full-scale output of 30 V, which exceeds the output range of the AD9610. Full-scale output voltage can be reduced by either reducing the DAC's full-scale output current, or by using a current divider at -6-
Power and Grounding Maintaining low noise on power supplies and ground is critical for obtaining optimum results with the AD9712 or AD9713. DACs are most often used in circuits which are predominantly digitaL To preserve 12-bit performance, especially at conversion speeds up to 100 MSPS, special precautions are necessary for power supplies and grounding. Ideally, the DAC should have a separate analog ground plane. All ground pins of the DAC, as well as reference and analog output components, should be tied directly to this analog ground plane. The DAC's ground plane should be connected to the system ground plane at a single point. Ferrite beads, along with high frequency, low inductance decoupiing capacitors, should be used for the supply connections ro isolate digital switching currents from the DAC supply pins. Separate isolation networks for the digital and analog supply connections will further reduce supply noise coupling to the oUtput. Molded socket assemblies should be avoided even when prototyping circuits with the AD9712 or AD9713. When the DAC cannot be directly soldered into the board, individual pin sockets such as AMP #6-330808-0 (knock-out end), or #60330808-3 (open end) should be used. These have much less effect on interlead capacitance than do molded assemblies. REV. A
ANALOGDEVICES fAX-ON-DEMAND HOTLINE
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AD9712/AD9713
-3S -40
-45 >-------3S 1MHz SINE WAVE -40 -45 -50 .1!-55 .. -60 SPURIOUS-FREE DYNAMIC RANGE
-60
.1!-55 .. -4iO -M -7\) -7$ 10
L 4TH HARMONICS
,/ AT NOISE F1.00R I I 80 100 20 40 80 UPDATE RATE (lISPS)
i
2ND, 3RD, AND
CSFDR)~
,/
-65 -70 -75 10
2ND, 3RD, AND 4TH HARMONICS AT NOI~E F1.00R I
i
60
60 100
AD9712 Harmonic Distortion vs. Update Rate
AD9713 Harmonic Distortion vs. Update Rate
-35 -40
-45
OBS -40 -45 -50
45
i--------
-so
i-55 -4iO -S L 3RO
-7\) -75
HARMONIC
i
10
20 40 80 UPDATERATE(MSPS)
AD9712 Harmonic Distortion vs. Update Rate
REFER
,-I
I
~
I -.. I_-tii
Output
CONTROL
~
OUT
OLE
.1!-55
-70 60 100 -7510
, , , .
.. -60 /2NDHARMONIC ~~:'~-:RMONIC -65 SADHARMONIC -
, 20 40 60 UPDATERATE(MSPS)
AD9713 Harmonic Distortion Ys. Update Rate
138 CURRENT SOUR
-
+
~
~~lLJ
Reference Input
TE
60 100
r
,
r---1
Reference
~~
~yf
ECLV-
-li.2Y
-li.2V
Control Amplifier Input
Full-Scale Current Control Loop
Control Amplifier Output
leu. "-
ECL Input Buffer
II
2R
2R II
II
"
2ft
"
2ft R
2.5kU
I"",
9
9
3OpI'
9
>2_1 -
TT1. IN
-$.2Y
R-2R DAC (for 6 LSBs)
-Va
ITL Input Buffer
Output Circut AD97121AD9713 Equivalent Circuits
REV. A
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ANALOGDEVICES FAX-ON-DEMANDHOTLINE
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30
AD971VAD9713
OUTLINE DIMENSIONS
Dimensions shown in inches and (rnm)
2S-Pin Plastic DIP (Suffix N)
0'> ex>
a
OBS
0.014111.112% (0.35610'-) D.IOOIISC (2.5411$C)
~I~= -11~._'~
~: : : : : : : : : : : ]~
1.38011.565 (35.101:1S.70) -10.01510.060 + + 0.1511
J ;I
~
~ (.)
t
IUI) MlN
H
~
D.70""X
(1.77 MAX)
t
Chip Carrier (Suffix P)
2S-Pin Plastic Leaded
LI- t ~~~:o;:~ ,..,
,(:4 ~ ii
~
!
TOP VIEW
~
(NOIIO-)
~
11
IZ
j.
(IU3i1t.S8) L..J OASOlG.- L.J U U L.J U 0---112.32112.57)
OLE
1
ae~
I
0.-430
f
...L (UI,:o.82)
0.lIIIO IISC
TII.Z7j) ...L 0.0131\).021
"
II
: LIO.Q2jIIO.03Z . IT (D.",,)
0.0"""-25
T
(o.331G..53)
(o..3IW.63)
0.025I0.OI(0.&411.01)
-o._nO(2.11112.79} -I O.le$;o.,OO 1(4.1"4.57)
TE
4. v> ::> ~ 0 UJ IZ a: 0..
-8-
REV. A
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